/*
 * Copyright (c) 2020 MediaTek Inc.
 *
 * Use of this source code is governed by a MIT-style
 * license that can be found in the LICENSE file or at
 * https://opensource.org/licenses/MIT
 */

#pragma once

/* come from CODA mipi_tx_config H file */

#define MIPITX_LANE_CON                    (0x0004UL)
#define MIPITX_VOLTAGE_SEL                (0x0008UL)
#define FLD_RG_DSI_PRD_REF_SEL              REG_FLD(6, 0)
#define FLD_RG_DSI_V2I_REF_SEL              REG_FLD(4, 10)
#define MIPITX_PRESERVED                (0x000CUL)
#define MIPITX_PLL_PWR                    (0x0028UL)
#define FLD_DA_DSI_PLL_SDM_PWR_ACK              REG_FLD(1, 8)
#define FLD_AD_DSI_PLL_SDM_ISO_EN               REG_FLD(1, 1)
#define FLD_AD_DSI_PLL_SDM_PWR_ON               REG_FLD(1, 0)
#define MIPITX_PLL_CON0                    (0x002CUL)
#define MIPITX_PLL_CON1                    (0x0030UL)
#define FLD_RG_DSI_PLL_EN                       REG_FLD(1, 0)
#define FLD_RG_DSI_PLL_POSDIV                   REG_FLD(3, 8)
#define FLD_RG_DSI_PLL_FBSEL                   REG_FLD(1, 13)
#define FLD_RG_DSI_PLL_DIV3_EN                   REG_FLD(1, 28)
#define MIPITX_PLL_CON2                    (0x0034UL)
#define FLD_RG_DSI_PLL_SDM_SSC_PRD              REG_FLD(16, 16)
#define FLD_RG_DSI_PLL_SDM_SSC_EN               REG_FLD(1, 1)
#define FLD_RG_DSI_PLL_SDM_SSC_PH_INIT          REG_FLD(1, 0)
#define MIPITX_PLL_CON3                    (0x0038UL)
#define FLD_RG_DSI_PLL_SDM_SSC_DELTA            REG_FLD(16, 16)
#define FLD_RG_DSI_PLL_SDM_SSC_DELTA1           REG_FLD(16, 0)
#define MIPITX_PLL_CON4                    (0x003CUL)
#define MIPITX_PHY_SEL0                    (0x0040UL)
#define FLD_MIPI_TX_CPHY2BC_SEL                 REG_FLD(4, 28)
#define FLD_MIPI_TX_PHY1_SEL                   REG_FLD(4, 24)
#define FLD_MIPI_TX_CPHY1CA_SEL                REG_FLD(4, 20)
#define FLD_MIPI_TX_PHYC_SEL                   REG_FLD(4, 16)
#define FLD_MIPI_TX_PHY1AB_SEL                 REG_FLD(4, 12)
#define FLD_MIPI_TX_PHY0_SEL                   REG_FLD(4, 8)
#define FLD_MIPI_TX_CPHY0BC_SEL                REG_FLD(4, 4)
#define FLD_MIPI_TX_PHY2_SEL                   REG_FLD(4, 0)
#define MIPITX_PHY_SEL1                    (0x0044UL)
#define FLD_MIPI_TX_CPHY_EN                    REG_FLD(1, 31)
#define FLD_MIPI_TX_CPHY2_HS_SEL               REG_FLD(2, 28)
#define FLD_MIPI_TX_CPHY1_HS_SEL               REG_FLD(2, 26)
#define FLD_MIPI_TX_CPHY0_HS_SEL               REG_FLD(2, 24)
#define FLD_MIPI_TX_LPRX0CA_SEL                REG_FLD(4, 20)
#define FLD_MIPI_TX_LPRX0BC_SEL                REG_FLD(4, 16)
#define FLD_MIPI_TX_LPRX0AB_SEL                REG_FLD(4, 12)
#define FLD_MIPI_TX_LPRX_SEL                   REG_FLD(4, 8)
#define FLD_MIPI_TX_CPHYXXX_SEL                REG_FLD(4, 4)
#define FLD_MIPI_TX_PHY3_SEL                   REG_FLD(4, 0)
#define MIPITX_PHY_SEL2                    (0x0048UL)
#define FLD_MIPI_TX_PHY2BC_HSDATA_SEL          REG_FLD(4, 28)
#define FLD_MIPI_TX_PHY1_HSDATA_SEL            REG_FLD(4, 24)
#define FLD_MIPI_TX_CPHY1CA_HSDATA_SEL         REG_FLD(4, 20)
#define FLD_MIPI_TX_PHYC_HSDATA_SEL            REG_FLD(4, 16)
#define FLD_MIPI_TX_PHY1AB_HSDATA_SEL          REG_FLD(4, 12)
#define FLD_MIPI_TX_PHY0_HSDATA_SEL            REG_FLD(4, 8)
#define FLD_MIPI_TX_CPHY0BC_HSDATA_SEL         REG_FLD(4, 4)
#define FLD_MIPI_TX_PHY2_HSDATA_SEL            REG_FLD(4, 0)
#define MIPITX_PHY_SEL3                    (0x004CUL)
#define FLD_MIPI_TX_PHY3_HSDATA_SEL            REG_FLD(4, 0)

#define MIPITX_D2_CKMODE_EN                (0x0120UL)
#define FLD_DSI_D2_CKMODE_EN               REG_FLD(1, 0)
#define MIPITX_D0_CKMODE_EN                (0x0220UL)
#define FLD_DSI_D0_CKMODE_EN               REG_FLD(1, 0)
#define MIPITX_CK_CKMODE_EN                (0x0320UL)
#define FLD_DSI_CK_CKMODE_EN               REG_FLD(1, 0)
#define MIPITX_D1_CKMODE_EN                (0x0420UL)
#define FLD_DSI_D1_CKMODE_EN               REG_FLD(1, 0)
#define MIPITX_D3_CKMODE_EN                (0x0520UL)
#define FLD_DSI_D3_CKMODE_EN               REG_FLD(1, 0)

#define MIPITX_D2_SW_CTL_EN                (0x015CUL)
#define FLD_DSI_D2_SW_CTL_EN               REG_FLD(1, 0)
#define MIPITX_D0_SW_CTL_EN                (0x025CUL)
#define FLD_DSI_D0_SW_CTL_EN               REG_FLD(1, 0)
#define MIPITX_CK_SW_CTL_EN                (0x035CUL)
#define FLD_DSI_CK_SW_CTL_EN               REG_FLD(1, 0)
#define MIPITX_D1_SW_CTL_EN                (0x045CUL)
#define FLD_DSI_D1_SW_CTL_EN               REG_FLD(1, 0)
#define MIPITX_D3_SW_CTL_EN                (0x055CUL)
#define FLD_DSI_D3_SW_CTL_EN               REG_FLD(1, 0)
